A conventional DC-DC switching converter has excellent conversion efficiency for heavy loading, yet has poor efficiency for light loading due to the switching loss under its constant switching frequency. A popular improvement is to employ a pulse-skipping mode (PSM) to remove the limitation of constant switching frequency to reduce the switching loss and thereby improve the conversion efficiency. However, this art introduce an accompanying problem. As the load reduces more and more, the switching frequency may decrease to an audible range, i.e. 20 Hz-20 kHz. Due to the piezoelectric effect of the capacitor's material, the instant switching current imparting on the capacitor will cause a large mechanical energy that brings about audio vibration and thereby undesirable noise. This phenomenon often happens to the input capacitor of a buck converter and the output capacitor of a boost converter.
The most forthright way to eliminate the audio noise is to limit the lowest boundary of the switching frequency, for example 25 kHz. However, doing this brings a burden to a constant on-time (COT) power converter. As shown in FIG. 1, a COT buck converter triggers the on-time Ton of the high-side switch when the output voltage Vout decreases to a preset valley point, and the on-time Ton is constant. At the end of the on-time Ton, the high-side switch is turned off, and until the output voltage Vout decreases to the valley point once more, the on-time Ton is triggered again. As loading decreases, the decreasing speed of the output voltage Vout becomes lower, so that the off-time Toff of the high-side switch becomes longer and thus the switching cycle Tsw becomes longer, i.e. lower switching frequency. Introduced with zero inductor current detection (ZCD), a COT power converter can generate PSM naturally, employing a constant on-time for the high-side switch and triggering the on-time for the next cycle at the valley point of the output voltage, for balance between the output current and the loading current, to regulate the output voltage at a preset level. However, at light loading state, due to the set lower limit to the switching frequency, the high-side switch will be turned on before the output voltage reaches the valley point, which necessarily causes the output current becoming greater than the loading current and thereby increasing the output voltage.
FIG. 2 is a waveform diagram of an inductor current of a conventional COT buck converter. For balance between the output current and the loading current in order to regulate the output voltage, each time the switching frequency decreases to the lower limit 25 kHz, or the switching cycle Tsw reaches the upper limit 40 μs, at time t1, the low-side switch is first turned on to allow the inductor current become negative, and until time t2, when the output voltage reaches the valley point, the constant on-time Ton is triggered. Then, at time t3 the high-side switch is turned off and the low-side switch is turned on, and until time t4, the inductor current decreases to zero, and the low-side switch is turned off, so a switching operation is finished. In this method, the net output of the positive and negative inductor currents is equal to the loading current, and the valley point of the output voltage can be maintained at the set value, while the negative inductor current results in degraded conversion efficiency, and the smaller the loading current is, the more significant the loss of the conversion efficiency is.
U.S. Pat. No. 7,652,461 provides a buck converter operating free of an audible frequency range, having the circuit as depicted in FIG. 3, which includes a pair of high-side switch M1 and low-side switch M2, a zero current detector 10, a comparator 12, an on-time circuit 14, a timer 16 and an on-time shaver 18. Once the zero current detector 10 detects the inductor current IL as zero, the low-side switch M2 is turned off to avoid negative inductor current, which otherwise will degrade the conversion efficiency of light loading. A reference voltage Vref determines the valley point of the output voltage Vout, and the comparator 12 compares a feedback voltage FB related to the output voltage Vout with the reference voltage Vref so that the signal S1 is pulled high when the feedback voltage FB decreases to cross over the reference voltage Vref, to trigger an SR flip-flop 20 to turn on the high-side switch M1. Then, after a time period, the on-time circuit 14 will reset the SR flip-flop 20 to turn off the on-time of the high-side switch M1. The timer 16 counts the off-time of the high-side switch M1, namely the sum of the on-time of the low-side switch M2 and the time when the switches M1 and M2 are both off. When loading is so light that the output voltage Vout decreases very slowly to thereby have the switching cycle Tsw reaching the preset upper limit, the timer 16 pulls high the signal S2 to forcibly trigger the SR flip-flop 20 to turn on the high-side switch M1, thereby preventing the switching frequency from decreasing to the audible range. For preventing the timer 16 from affecting stability of the output voltage Vout, an offset voltage Voff1 is set in the on-time shaver 18. When the feedback voltage FB is greater than the sum of the offset voltage Voff1 and the reference voltage Vref, a transconductance amplifier 22 outputs a current positively proportional to Voff1+Vref-FB, which is multiplied by the output voltage Vout and then sent to the on-time circuit 14 for changing the threshold of the on-time circuit 14, to shave the on-time of the high-side switch M1, thereby decreasing the inductor current IL for balance to the loading current. By eliminating negative inductor current, this art provides better efficiency for light loading. However, the output voltage Vout will be related to the open-loop gain of the transconductance amplifier 22.